The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device having a multi-bank structure.
In a dynamic random access memory (DRAM), a memory density is increasing from 256M to 512M and from 512M to 1 G so as to improve cost performance. Further, a bank structure supported by the DRAM is changing from a 4-bank structure to an 8-bank structure and from an 8-bank structure to a 16-bank structure.
There are limitations in increasing the memory density and the multi-bank. In this regard, write global input/output (I/O) lines (WGIO_IO), write global core lines (WGIO_CORE), read global core lines (RGIO_CORE), and read global I/O lines (RGIO_IO) will be described below. External data are transferred to cells of a designated bank through the write global I/O lines (WGIO_IO) and the write global core lines (WGIO_CORE). Data stored in cells of a designated bank are transferred to external circuits through the read global core lines (RGIO_CORE) and the read global I/O lines (RGIO_IO).
FIG. 1 is a layout diagram of a conventional 512 MB DRAM having eight banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6 and BANK7. The DRAM of FIG. 1 operates in an x32 operation mode to read/write 32 bits of data in each column operation. The DRAM includes thirty-two DQ pads for the x32 operation mode. In addition, the DRAM has a 4-bit prefetch architecture.
Meanwhile, the DRAM is designed to have I/O paths with a multi-bit structure according to data option modes, e.g., x4, x8, x16, x32, etc. Hence, the semiconductor memory devices may be differently configured even though they have the same capacity. In other words, after the semiconductor device is designed and fabricated such that it satisfies all of the x4, x8, x16, and x32 operation modes, the semiconductor memory device is configured such that it operates in the x4, x8, x16, or x32 operation mode according to a selected option.
Referring to FIG. 1, the 512 MB DRAM is divided into four quarters QA, QB, QC and QD. The four 128 MB quarters QA, QB, QC and QD read or write data through corresponding ones of pads DQ<0:31>. That is, the quarter QA reads or writes data through the pads DQ<0:7>, the quarter QB reads or writes data through the pads DQ<8:15>, the quarter QC reads or writes data through the pads DQ<16:23>, and the quarter QD reads or writes data through the pads DQ<24:31>.
In the case of the write operation in the x32 operation mode, data inputted through all of the pads DQ<0:31> are inputted to the corresponding bank of the quarters QA, QB, QC and QD, that is, one of the banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6 and BANK7. In the case of the read operation in the x32 operation mode, 32-bit data are outputted from the corresponding bank of the quarters QA, QB, QC and QD, that is, one of the banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6 and BANK7, through the corresponding pads DQ<0:31>.
Meanwhile, a strobe decoder 10 is disposed in the center of the chip and outputs bank strobe signals MSTROBE_BANK<0:7> to center portions 20A, 20B, 20C and 20D of the respective quarters QA, QB, QC and QD so as to enable the corresponding banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6 and BANK7. Although each of the center portions 20A, 20B, 20C and 20D of the respective quarters QA, QB, QC and QD is indicated by one block in FIG. 1, each of them includes a read/write strobe signal generator receiving the bank strobe signals MSTROBE_BANK<0:7>, an input data buffer, and an output data buffer, which will be described later with reference to FIGS. 3, 4 and 5, respectively.
FIG. 2 is a block diagram of the strobe decoder 10 illustrated in FIG. 1.
Referring to FIG. 2, the strobe decoder 10 receives a column strobe signal STROBE_PRE and bank information CAST<0:2> on eight banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6 and BANK7 to output bank strobe signals MSTROBE_BANK<0:7>. The column strobe signal STROBE_PRE is a signal that is activated during a column operation in the read/write operations.
FIG. 3 is a circuit diagram of the read/write strobe signal generator illustrated in FIG. 1.
Referring to FIG. 3, the read/write strobe signal generator 23A receives a read/write signal WTRZT and the bank strobe signals MSTROBE_BANK<0:7>, e.g., MSTROBE_BANK<0> for enabling the bank BANK0, and outputs a read strobe signal RSTROBE_BANK<0> and a write strobe signal WSTROBE_BANK<0> corresponding to the bank BANK0.
The read/write signal WTRZT becomes a logic high level in the write operation and a logic low level in the read operation. When the read or write operation is determined, the read strobe signals RSTROBE_BANK<0:7> or the write strobe signals WSTROBE_BANK<0:7> corresponding to the respective banks are generated according to the bank strobe signals MSTOBE_BANK<0:7>. Then, the selected banks are enabled and the read/write operations are performed thereto.
The strobe signal generator 23A includes first and second delay units D1 and D2 in order for a more stable timing matching of the read strobe signals RSTROBE_BANK<0:7>and the write strobe signals WSTROBE_BANK<0:7>in the read/write operations.
The structure and operation of the conventional DRAM will be described in more detail with reference to FIG. 1.
For convenience, the DRAM will be described centering on the quarter QA. The write global I/O lines WGIO_IO_EV0<0:7>, WGIO_IO_OD0<0:7>, WGIO_IO_EV1<0:7> and WGIO_IO_OD1<0:7>, and the read global I/O lines RGIO_IO_EV0<0:7>, RGIO_IO_OD0<0:7>, RGIO_IO_EV1<0:7> and RGIO_IO_OD1<0:7> are connected to the pads DQ<0:7> corresponding to the quarter QA. The write global core lines WGIO_CORE_EV0<0:7>, WGIO_CORE_OD0<0:7>, WGIO_CORE_EV1<0:7> and WGIO_CORE_OD1<0:7>, and the read global core lines RGIO_CORE_EV0<0:7>, RGIO_CORE_OD0<0:7>, RGIO_CORE_EV1<0:7> and RGIO_CORE_OD1<0:7> are connected to the respective banks. Those lines are provided for the 4-bit prefetch operation. In the following description, the prefetch operation will be omitted. That is, the following description will be focused on the “WGIO_IO_EV0<0:7>” line of the write global I/O lines WGIO_IO_EV<0:7>, WGIO_IO_ODD0<0:7>, WGIO_IO_EV1<0:7> and WGIO_IO_OD1<0:7>, and the “WGIO_CORE_EV0<0:7> line of the write global core lines WGIO_CORE_EV0<0:7>, WGIO_CORE_OD0<0:7>, WGIO_CORE_EV1<0:7> and WGIO_CORE_OD1<0:7> for transferring data in the write operation. In addition, the following description will be focused on the “RGIO_CORE_EV0<0:7> line of the read global core lines RGIO_CORE_EV0<0:7>, RGIO_CORE_OD0<0:7>, RGIO_CORE_EV1<0:7> and RGIO_CORE_OD1<0:7>, and the “RGIO_IO_EV0<0:7> line of the read global I/O lines RGIO_IO_EV0<0:7>, RGIO_IO_OD0<0:7>, RGIO_IO_EV1<0:7> and RGIO_IO_OD1<0:7> for transferring data in the read operation.
In the write operation, external 8-bit data for the bank of the quarter QA are inputted through the pads DQ<0:7> to the write global I/O lines WGIO_IO_EV0<0:7>. The input data are inputted to an input data buffer and then transferred through the write global core lines WGIO_CORE_EV0<0:7> to the corresponding enabled bank.
FIG. 4 is a circuit diagram of the input data buffer 21A illustrated in FIG. 1. For convenience, the input data buffer 21A will be described centering on the “WGIO_IO_EV0<0> line of the write global I/O lines WGIO_IO_EV0<0:7> and the “WGIO_CORE_EV0<0> line of the write global core lines WGIO_CORE_EV0<0:7>.
Referring to FIG. 4, the input data buffer 21A includes inverters INV1 and INV2 for buffering data inputted through the write global I/O line WGIO_IO_EV0<0>, and inverters INV3 and INV4 for repeating the buffered data. The input data buffer 21A outputs the data to the write global core line WGIO_CORE_EV0<0>.
Next, the read operation will be described below with reference to FIG. 1.
8-bit data of the bank BANK0 are inputted to the read data buffer through the read global core lines RGIO_CORE_EV0<0:7>, and an output signal of the read data buffer is transferred through the read global I/O line RGIO_IO_EV0<0:7> to the corresponding pads DQ<0:7>.
FIG. 5 is a circuit diagram of the output data buffer 22A illustrated in FIG. 1. For convenience, the output data buffer will be described centering on the “RGIO_IO_EV0<0> line of the read global I/O lines RGIO_IO_EV0<0:7> and the “RGIO_CORE_EV0<0> line of the read global core lines RGIO_CORE_EV0<0:7>.
Referring to FIG. 5, the output data buffer 22A includes inverters INV5 and INV6 for repeating data inputted through the read global core lines RGIO_CORE_EV0<0>, and inverters INV7 and INV8 for buffering the inputted data. The output data buffer 22A outputs the buffered data to the read global I/O lines RGIO_IO_EV0<0>.
As the memory density is changing from 512 MB to 1 GB and the multi-bank structure is changing from an 8-bank structure to a 16-bank structure, the loading and junction of the respective global lines in the conventional structure increase more than two times. Therefore, data transferred through the respective global lines experience a timing delay and a voltage level is sloped. Consequently, the semiconductor device cannot operate normally.
Further, the number of the bank strobe signals MSTROBE_BANK<0:7> outputted from the strobe decoder 10 that is disposed in the middle of the chip, that is, the peripheral region, increases with increase of number of the banks. The number of the global lines transferring the signals also increases and the shielding lines increases. Consequently, the layout area increases.